WRITEBACK_INSTRS=WRITEBACK_INSTRS_0, UNPRIV_INSTRS=UNPRIV_INSTRS_0, WITHSHIFTS_INSTRS=WITHSHIFTS_INSTRS_0, PSR_M_INSTRS=PSR_M_INSTRS_0, BARRIER_INSTRS=BARRIER_INSTRS_0
Instruction Set Attributes Register 4
| UNPRIV_INSTRS | Indicates the supported unprivileged instructions. These are the instruction variants indicated by a T suffix. 0 (UNPRIV_INSTRS_0): None supported, ARMv7-M unused. 1 (UNPRIV_INSTRS_1): Adds support for the LDRBT, LDRT, STRBT, and STRT instructions. 2 (UNPRIV_INSTRS_2): As for 1, and adds support for the LDRHT, LDRSBT, LDRSHT, and STRHT instructions. |
| WITHSHIFTS_INSTRS | Indicates the support for instructions with shifts 0 (WITHSHIFTS_INSTRS_0): Nonzero shifts supported only in MOV and shift instructions. 1 (WITHSHIFTS_INSTRS_1): Adds support for shifts of loads and stores over the range LSL 0-3. 3 (WITHSHIFTS_INSTRS_3): As for 1, and adds support for other constant shift options, on loads, stores, and other instructions. 4 (WITHSHIFTS_INSTRS_4): ARMv7-M unused. |
| WRITEBACK_INSTRS | Indicates the support for Writeback addressing modes 0 (WRITEBACK_INSTRS_0): Basic support. Only the LDM, STM, PUSH, and POP instructions support writeback addressing modes. ARMv7-M unused. 1 (WRITEBACK_INSTRS_1): Adds support for all of the writeback addressing modes defined in the ARMv7-M architecture. |
| BARRIER_INSTRS | Indicates the supported Barrier instructions 0 (BARRIER_INSTRS_0): None supported, ARMv7-M unused. 1 (BARRIER_INSTRS_1): Adds support for the DMB, DSB, and ISB barrier instructions. |
| SYNCHPRIM_INSTRS_FRAC | Together with the ID_ISAR3[SYNCHPRIM_INSTRS] indicates the supported Synchronization Primitives |
| PSR_M_INSTRS | Indicates the supported M profile instructions to modify the PSRs 0 (PSR_M_INSTRS_0): None supported, ARMv7-M unused. 1 (PSR_M_INSTRS_1): Adds support for the M-profile forms of the CPS, MRS, and MSR instructions, to access the PSRs. |